Three-dimensional integrated circuits (3-D ICs) have been shown to reduce on-chip global interconnect lengths and thus alleviate delay and power consumption problems. 3-D ICs can also facilitate the integration of dissimilar technologies (digital, analog, radio-frequency circuits, et al.). In a 3-D IC, multiple active layers or dies are vertically stacked on top of each other and are interconnected using “short” vertical links. These “short” vertical links are referred to as through-silicon vias (TSVs).
While 3-D ICs provide many benefits, such benefits can be realized only when major challenges in the areas of design, manufacture and test are addressed. In traditional IC testing, wafers are probed and individual dies tested before they are packaged. For 3-D ICs, both pre-bond testing and post-bond testing of wafers are needed to increase the yield. An important aspect for the post-bond testing is testing of TSVs because TSVs are key components of a 3-D IC, providing power, clock and functional signals. Even a single TSV defect between any two layers of a 3-D IC chip stack can void the entire chip stack, reducing the overall yield. Capability of testing interconnections between stacked dies should be included in any test architecture in a circuit design.
Another important aspect for the post-bond testing is test access. One or more test interface ports must be established through the bottom die to allow test of any die in the stack and of the interconnections between the dies. Only a limited number of TSVs, however, can be reserved for use by the testing circuitry. This is because the total number of TSVs on a die is limited due to the need for a “keep-out” area and most of these TSVs are required for power, clock, and signal lines.
It is thus desirable to design a test access architecture that provides efficient test access and control through a small number of dedicated TSVs for both individual die testing and interconnection testing.